Quantcast
[ 3 / biz / cgl / ck / diy / fa / g / ic / jp / lit / sci / tg / vr / vt ] [ index / top / reports / report a bug ] [ 4plebs / archived.moe / rbt ]

/vt/ is now archived.Become a Patron!

/g/ - Technology

Search:


View post   

[ Toggle deleted replies ]
>> No.58841912 [View]
File: 95 KB, 680x719, TDF-TSMC-16nm-Ge-finFET-IEDM-diag-2-med.jpg [View same] [iqdb] [saucenao] [google] [report]
58841912

>>58841871
Cross section of a back end.

>> No.55102347 [View]
File: 95 KB, 680x719, TDF-TSMC-16nm-Ge-finFET-IEDM-diag-2-med.jpg [View same] [iqdb] [saucenao] [google] [report]
55102347

>>55102170
The shape of a die is dictated almost entirely by the structures featured. You have a little bit of wiggle room with how things are placed, and how dense the logic is in certain spots, but you can't radically alter the layout. Everything on the front end of line is connected on the back end of line. You can't arbitrarily rearrange complex logic.

>> No.46103917 [View]
File: 95 KB, 680x719, TDF-TSMC-16nm-Ge-finFET-IEDM-diag-2-med.jpg [View same] [iqdb] [saucenao] [google] [report]
46103917

>>46103856
Not happening any time soon.
Intel internally developed their chips around their process nodes at the same time, a 3rd party coming in and trying to confirm to their process is going to be a hard learning process for all parties involved.


>>46103872
lithography is a complex thing, incredibly complex. From the wafer to the back end of line, to the gates themselves. Every single link in the chain has its own nuances and intricacies that include the potential to do thousands of things wrong.



Navigation
View posts [+24] [+48] [+96]