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>> No.58857914 [View]
File: 144 KB, 1280x960, ed9de1d1998f3a266cb38f16eb1971ba_1377810701.jpg [View same] [iqdb] [saucenao] [google] [report]
58857914

>>58857842
Oh boy, I haven't heard this exact line of violent stupidity before. No foundry lies about anything regarding front end feature size. Not intel, not Samsung, not TSMC, not Global Foundries, not UMC, not any of the dinky small 90nm fabs still up and running. No one.
Your inability to understand a public facing marketing name is not their problem.

>>58857869
Stupid little fanboy bitching about meaningless back end area scaling right on cue.
Samsung and TSMC's 14/16nm nodes are their "transitional" FinFET nodes. They use a smaller front end on an existing back end to reduce the cost of bringing a smaller node online. The density of the back end does not impact the electrostatic characteristics of the transistors on the front end. All it impacts is area scaling, the number of candidates per wafer.

Global Foundries' 7nm process is an advanced SOI based FinFET node, radically different from the bulk silicon FinFETs used across the industry today. Intel is falling far behind the industry when even TSMC and Samsung will be using GAA devices before intel has a single 7nm test chip on hand.

>> No.58373125 [View]
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58373125

>>58373013
Challenges in structures:
More complex shapes, more electrical routing, these require more masks to be used when producing a chip. As the demand for higher performance and lower power increase we're having to explore more exotic arrangements. Naturally if follows that exotic things tend to not be simple. Having a design utilize 40, 50, possibly even more masks is now becoming a reality. Every pass introduces the potential for a small flaw, and that flaw can get magnified in each successive layer. Again yields suffer. The less viable candidates per wafer the more expensive those remaining good dies are.
We've transitioned from relatively simple 2D gates, to current FinFETs, and that is the perfect case to examine some issues inherent to bulk silicon.

With bulk based structures you have a higher degree of doping required, you inherently need more masks to build up base isolation structures for critical areas of the transistor vs a device built on an SOI wafer. Each has its own set of advantages and disadvantages, but SOI structures are simpler.
The doping of the wafer itself is a vital step, and one of bulk's biggest downsides. Dopants need to be distributed with atomic level precision, a single misplaced atom can adversely impact the entire transistor built ontop of it.
https://www.youtube.com/watch?v=k0J_y0Av_f8

>> No.55304759 [View]
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55304759

>>55304716
Also worth noting:
There is a very strong chance that POWER9 is 14nm FinFET utilizing an internally developed SOI based FinFET process. The chips will be fabbed by Global Foundries who recently acquired IBM's fab business along with a host of IP, and engineers.



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