/diy/ - Do It Yourself

>>1944013
FPGA are often thought about as a bunch of flipflops and logic gates interconnected in a way that's configurable. In reality, logic gates aren't accessable. Instead, there's "logic blocks" made of LUTs (look up tables), with typically 4 inputs, and a flipflop that can be bypassed between LUT and output.
The logic block's configuration (truth table, flipflop initial value, whether to bypass it) and the interconnects between blocks (logic blocks, I/O ports, embedded memories, clocks...) are what's "programmed" into the chip.
This "programming" depends on the chip design. On some chips it is SRAM, and needs to be done in power-on, on some other chips it is "flash", and thus the design is immediately available on power on.
While at the start, in the 80s, it was sometimes done that way, nobody designs the FPGA configuration directly. Instead, what is done is writing your design in an HDL. The most common are Verilog and VHDL.
Then a synthesis tool turns the HDL into something much simpler, similar to how a compiler turns c code into assembler. The primary open stack tool for synthesis is Yosys.
This simpler hardware description or netlist then goes through placing and routing, which is very specific to the target chip, which can be an FPGA or an ASIC. The primary open stack tool for PNR is openpnr. This is basically a process of allocating physical logic blocks to what's described in the netlist, considering the constraints of the hardware. For FPGAs, this includes where blocks and wires are physically placed. For ASICs, it's more like what constraints the fabrication process imposes to where they can be physically placed.
To answer your question: Yes, the same HDL can be programmed into FPGAs or made into ASICs. No, it doesn't work by taking an xray of the FPGA, but the process I described above.
If you want to learn more about FPGAs, your best bet would be to grab a iCESugar from Aliexpress (cheap!) and/or an ULX3S from elsewhere (powerful! featureful!).